arch_cache.h — CPU Cache 控制接口头文件

源文件路径: arch/arm/armv7m/include/arch_cache.h

引用章节: 4.1 内核简介

完整源码

/**
 ***********************************************************************************************************************
 * Copyright (c) 2020, China Mobile Communications Group Co.,Ltd.
 *
 * Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with
 * the License. You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
 * an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
 * specific language governing permissions and limitations under the License.
 *
 * @file        arch_cache.h
 *
 * @brief       Header file for cache interface.
 *
 * @revision
 * Date         Author          Notes
 * 2020-02-23   OneOS Team      First version.
 ***********************************************************************************************************************
 */

#ifndef __ARCH_CACHE_H__
#define __ARCH_CACHE_H__

#include <os_types.h>

#ifdef __cplusplus
extern "C" {
#endif

enum OS_HW_CACHE_OPS
{
    OS_HW_CACHE_FLUSH      = 0x01,
    OS_HW_CACHE_INVALIDATE = 0x02,
};

extern void      os_cpu_icache_enable(void);
extern void      os_cpu_icache_disable(void);
extern os_base_t os_cpu_icache_status(void);
extern void      os_cpu_icache_ops(int32_t ops, void *addr, int32_t size);

extern void      os_cpu_dcache_enable(void);
extern void      os_cpu_dcache_disable(void);
extern os_base_t os_cpu_dcache_status(void);
extern void      os_cpu_dcache_ops(int32_t ops, void *addr, int32_t size);

#ifdef __cplusplus
}
#endif

#endif /* __ARCH_CACHE_H__ */

关键说明

模块	说明
操作类型	OS_HW_CACHE_FLUSH（0x01）清除并写回，OS_HW_CACHE_INVALIDATE（0x02）无效化，可组合使用
I-Cache	指令缓存控制：enable/disable/status 控制启停和状态查询，ops 执行指定范围操作
D-Cache	数据缓存控制：enable/disable/status 控制启停和状态查询，ops 执行指定范围操作
适用架构	ARMv7-M 通常无 Cache（Cortex-M3/M4 无内置 Cache），但 Cortex-M7/M55 等含 Cache 的 M 核需要此接口
DMA 一致性	在 DMA 操作前后需要调用 os_cpu_dcache_ops